Jacques Benkoski

According to our database1, Jacques Benkoski authored at least 14 papers between 1987 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2007
Do Digital Design and Variability Mix like Oil and Water?
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2002
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs.
Proceedings of the 2002 Design, 2002

2001
0.13 micron: Will the Speed Bumps Slow the Race to Market?
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
How Do You Select A High Quality EDA Tool Flow?.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1993
Demosthenes-A technology-independent power DMOS layout generator.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation.
Proceedings of the conference on European design automation, 1992

1991
Static Timing Analysis Using Interval Constraints.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator.
Proceedings of the conference on European design automation, 1991

TATOO: an industrial timing analyzer with false path elimination and test pattern generation.
Proceedings of the conference on European design automation, 1991

The Role of Timing Verification in Layout Synthesis.
Proceedings of the 28th Design Automation Conference, 1991

1990
Timing verification using statically sensitizable paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator.
Proceedings of the Proceedings International Test Conference 1989, 1989

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987
A New Approach to Hierarchical and Statistical Timing Simulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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