Andrzej J. Strojwas

According to our database1, Andrzej J. Strojwas authored at least 72 papers between 1982 and 2023.

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Awards

IEEE Fellow

IEEE Fellow 1991, "For contributions to statistically-based computer-aided manufacturing of integrated circuits.".

Timeline

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Bibliography

2023
In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2019
Yield and Reliability Challenges at 7nm and Below.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2016
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2014
Sub-20 nm design technology co-optimization for standard cell logic.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Automatic clustering of wafer spatial signatures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011
Cost effective scaling to 22nm and below technology nodes.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Who solves the variability problem?
Proceedings of the 47th Design Automation Conference, 2010

2009
Creating an affordable 22nm node using design-lithography co-optimization.
Proceedings of the 46th Design Automation Conference, 2009

2007
DFM/DFY: should you trust the surgeon or the family doctor?
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Guest Editors' Introduction: DFM Drives Changes in Design Flow.
IEEE Des. Test Comput., 2005

Statistical Critical Path Analysis Considering Correlations.
Proceedings of the Integrated Circuit and System Design, 2005

Tutorial on DFM for physical design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Projection-based performance modeling for inter/intra-die variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Correlation-aware statistical timing analysis with non-gaussian delay distributions.
Proceedings of the 42nd Design Automation Conference, 2005

Design methodology for IC manufacturability based on regular logic-bricks.
Proceedings of the 42nd Design Automation Conference, 2005

2004
When IC yield missed the target, who is at fault?
Proceedings of the 41th Design Automation Conference, 2004

Routing architecture exploration for regular fabrics.
Proceedings of the 41th Design Automation Conference, 2004

2003
Global and local congestion optimization in technology mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Bounding the efforts on congestion optimization for physical synthesis.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Exploring regular fabrics to optimize the performance-cost trade-off.
Proceedings of the 40th Design Automation Conference, 2003

2002
Understanding and addressing the impact of wiring congestion during technology mapping.
Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion-Aware Logic Synthesis.
Proceedings of the 2002 Design, 2002

2001
Path delay fault diagnosis and coverage-a metric and an estimationtechnique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Primitive path delay faults: identification and their use in timinganalysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Perspectives on technology and technology-driven CAD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Design-Manufacturing Interface for 0.13 Micron and Below.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

When bad things happen to good chips (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

Impact of interconnect variations on the clock skew of a gigahertz microprocessor.
Proceedings of the 37th Conference on Design Automation, 2000

Design for manufacturability: a path from system level to high yielding chips: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000

1999
An algorithm for determining repetitive patterns in very large IC layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A New Methodology for Concurrent Technology Development and Cell Library Optimization.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Model Order-Reduction of RC(L) Interconnect Including Variational Analysis.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A pattern matching algorithm for verification and analysis of very large IC layouts.
Proceedings of the 1998 International Symposium on Physical Design, 1998

<i>ftd</i>: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Primitive Path Delay Fault Identification.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Timing analysis based on primitive path delay fault identification.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
A diagnosability metric for parametric path delay faults.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Diagnosis of parametric path delay faults.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Manufacturability of low power CMOS technology solutions.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Test Vector Generation for Parametric Path Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Stochastic Interpolation Model Scheme for Statistical Circuit Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Towards Incorporating Device Parameter Variations in Timing Analysis.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Variable Accuracy Device Modeling for Event-Driven Circuit Simulation.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

MONSTR: A Complete Thermal Simulator of Electronic Systems.
Proceedings of the 31st Conference on Design Automation, 1994

1993
The CDB/HCDB semiconductor wafer representation server.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Numerical integral method for diffusion modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An efficient algorithm for parametric fault simulation of monolithic IC's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator.
Proceedings of the 28th Design Automation Conference, 1991

Utilizing Logic Information in Multi-Level Timing Simulation.
Proceedings of the 28th Design Automation Conference, 1991

The Role of Timing Verification in Layout Synthesis.
Proceedings of the 28th Design Automation Conference, 1991

1990
Statistical control of VLSI fabrication processes.
Proc. IEEE, 1990

1989
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator.
Proceedings of the Proceedings International Test Conference 1989, 1989

Design for Manufacturability and Yield.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987
Realistic Yield Simulation for VLSIC Structural Failures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A New Approach to Hierarchical and Statistical Timing Simulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986
A Statistical Design Rule Developer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

A Methodology for Worst-Case Analysis of Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

VLSI Yield Prediction and Estimation: A Unified Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

The CMU-CAM System.
IEEE Des. Test, 1986

Yield of VLSI circuits: myths vs. reality (panel).
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
A Pattern Recognition Based Method for IC Failure Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

PROD: A VLSI Fault Diagnosis System.
IEEE Des. Test, 1985

1984
FABRICS II: A Statistically Based IC Fabrication Process Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1982
Statistical Simulation of the IC Manufacturing Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982


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