Carlo Guardiani

Orcid: 0000-0002-8914-9260

According to our database1, Carlo Guardiani authored at least 27 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Integrated Approach Including Docking, MD Simulations, and Network Analysis Highlights the Action Mechanism of the Cardiac hERG Activator RPR260243.
J. Chem. Inf. Model., August, 2023

2021
Application of a Statistical and Linear Response Theory to Multi-Ion Na+ Conduction in NaChBac.
Entropy, 2021

2020
Changes in Ion Selectivity Following the Asymmetrical Addition of Charge to the Selectivity Filter of Bacterial Sodium Channels.
Entropy, 2020

2007
DFM/DFY: should you trust the surgeon or the family doctor?
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Yield-aware placement optimization.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
DFM rules!
Proceedings of the 42nd Design Automation Conference, 2005

An effective DFM strategy requires accurate process and IP pre-characterization.
Proceedings of the 42nd Design Automation Conference, 2005

2004
High Yield Standard Cell Libraries: Optimization and Modeling.
Proceedings of the Integrated Circuit and System Design, 2004

Proactive design for manufacturing (DFM) for nanometer SoC designs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Sympatric Speciation Through Assortative Mating in a Long-Range Cellular Automaton.
Proceedings of the Cellular Automata, 2004

2002
Impact Analysis of Process Variability on Clock Skew.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Analog IP Testing: Diagnosis and Optimization.
Proceedings of the 2002 Design, 2002

2001
Modeling of Substrate Noise Injected by Digital Libraries.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Design for manufacturability characterization and optimization of mixed-signal IP.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning.
Proceedings of the 36th Conference on Design Automation, 1999

Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Power invariant vector compaction based on bit clustering and temporal partitioning.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Automatic characterization and modeling of power consumption in static RAMs.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Nonlinear macromodels of large coupled interconnect networks.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs.
Proceedings of the ASP-DAC '98, 1998

1997
Accurate and Efficient Macromodel of Submicron Digital Standard Cells.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Manufacturability of low power CMOS technology solutions.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells.
Proceedings of the 32st Conference on Design Automation, 1995


  Loading...