Jaehun Jun
Orcid: 0000-0001-5285-7063
According to our database1,
Jaehun Jun
authored at least 8 papers
between 2017 and 2020.
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Bibliography
2020
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system.
IET Circuits Devices Syst., 2020
2019
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
2018
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations.
Proceedings of the International SoC Design Conference, 2017