Yoonjae Choi
Orcid: 0000-0003-0594-4206
According to our database1,
Yoonjae Choi
authored at least 25 papers
between 2013 and 2024.
Collaborative distances:
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Bibliography
2024
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.
IEEE J. Solid State Circuits, April, 2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024
2023
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces.
IEEE J. Solid State Circuits, 2023
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits, 2023
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations.
IEEE J. Solid State Circuits, 2022
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE J. Solid State Circuits, 2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits, 2021
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access, 2021
2019
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits, 2019
2018
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
Extracting Events from Web Documents for Social Media Monitoring Using Structured SVM.
IEICE Trans. Inf. Syst., 2013