James B. Kuo
According to our database1,
James B. Kuo
authored at least 30 papers
between 1989 and 2014.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2000, "For contributions to modeling CMOS VLSI devices.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2014
Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2011
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
2010
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect.
Microelectron. Reliab., 2010
Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2005
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
2003
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme.
IEEE J. Solid State Circuits, 2002
2001
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques.
IEEE J. Solid State Circuits, 2001
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell.
IEEE J. Solid State Circuits, 2001
2000
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1998
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI.
IEEE J. Solid State Circuits, 1997
1996
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit.
IEEE J. Solid State Circuits, August, 1995
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology.
IEEE J. Solid State Circuits, January, 1995
1994
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1992
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition.
Neural Networks, 1992
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989