Bruce A. Wooley

Affiliations:
  • Stanford University, USA


According to our database1, Bruce A. Wooley authored at least 65 papers between 1973 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
A low noise current readout architecture for fluorescence detection in living subjects.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Zero-pole modulation and demodulation for noise reduction in charge amplifiers.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A High-Resolution Low-Power Incremental Sigma Delta ADC With Extended Range for Biosensor Arrays.
IEEE J. Solid State Circuits, 2010

A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 5-GHz Wireless LAN Transmitter with Integrated Tunable High-Q RF Filter.
IEEE J. Solid State Circuits, 2009

A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator.
IEEE J. Solid State Circuits, 2009

Design and implementation of a CMO 802.11n SoC.
IEEE Commun. Mag., 2009

2008
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN.
IEEE J. Solid State Circuits, 2008

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator.
IEEE J. Solid State Circuits, 2008

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth.
IEEE J. Solid State Circuits, 2008


2007
A Digitally Modulated Polar CMOS PA with 20MHz Signal BW.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 1.9-GHz Single-Chip CMOS PHS Cellphone.
IEEE J. Solid State Circuits, 2006

A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems.
IEEE J. Solid State Circuits, 2006

An IEEE 802.11a/b/g SoC for Embedded WLAN Applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1.9GHz Single-Chip CMOS PHS Cellphone.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion.
IEEE J. Solid State Circuits, 2005

An 802.11g WLAN SoC.
IEEE J. Solid State Circuits, 2005

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC.
IEEE J. Solid State Circuits, 2005

2004
A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN.
IEEE J. Solid State Circuits, 2004

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS.
IEEE J. Solid State Circuits, 2004

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering.
IEEE J. Solid State Circuits, 2004

A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling.
IEEE J. Solid State Circuits, 2003

A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system.
IEEE J. Solid State Circuits, 2003

Cascaded noise-shaping modulators for oversampled data conversion.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems.
IEEE J. Solid State Circuits, 2002

A CMOS RF power amplifier with parallel amplification for efficient power control.
IEEE J. Solid State Circuits, 2002

2001
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver.
IEEE J. Solid State Circuits, 2001

A 2.5-V sigma-delta modulator for broadband communications applications.
IEEE J. Solid State Circuits, 2001

A 15-b pipelined CMOS floating-point A/D converter.
IEEE J. Solid State Circuits, 2001

2000
A two-path bandpass sigma-delta modulator with extended noise shaping.
IEEE J. Solid State Circuits, 2000

1999
The efficiency of methods for measuring A/D converter linearity.
IEEE Trans. Instrum. Meas., 1999

A BiCMOS active substrate probe-card technology for digital testing.
IEEE J. Solid State Circuits, 1999

A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation.
IEEE J. Solid State Circuits, 1999

1998
A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter.
IEEE J. Solid State Circuits, 1998

Explanation component of software system.
XRDS, 1998

Pronoun Resolution of "They" and "Them".
Proceedings of the Eleventh International Florida Artificial Intelligence Research Society Conference, 1998

1997
A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS.
IEEE J. Solid State Circuits, 1997

A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz.
IEEE J. Solid State Circuits, 1997

1996
A 900-MHz RF front-end with integrated discrete-time filtering.
IEEE J. Solid State Circuits, 1996

A 250-MHz skewed-clock pipelined data buffer.
IEEE J. Solid State Circuits, 1996

A 1.3-ns 32-word×32-bit three-port BiCMOS register file.
IEEE J. Solid State Circuits, 1996

A 128×128-pixel standard-CMOS image sensor with electronic shutter.
IEEE J. Solid State Circuits, 1996

1995
A CMOS multichannel IC for pulse timing measurements with 1-mV sensitivity.
IEEE J. Solid State Circuits, December, 1995

The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
A BiCMOS time interval digitizer based on fully-differential, current-steering circuits.
IEEE J. Solid State Circuits, June, 1994

A low-power, area-efficient digital filter for decimation and interpolation.
IEEE J. Solid State Circuits, June, 1994

A 700-MHz switched-capacitor analog waveform sampling circuit.
IEEE J. Solid State Circuits, April, 1994

A third-order sigma-delta modulator with extended dynamic range.
IEEE J. Solid State Circuits, March, 1994

1989
Two-dimensional transient analysis of a collector-up ECL inverter.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Simulating and testing oversampled analog-to-digital converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986
Two CMOS Metastability Sensors.
Proceedings of the Proceedings International Test Conference 1986, 1986

1983
Stabilized biasing of semiconductor lasers.
Bell Syst. Tech. J., 1983

1981
A Voiceband Codec with Digital Filtering.
IEEE Trans. Commun., 1981

1979
An Integrated Per-Channel PCM Encoder Based on Interpolation.
IEEE Trans. Commun., 1979

An Integrated Interpolative PCM Decoder.
IEEE Trans. Commun., 1979

1976
A Per-Channel A/D Converter Having 15-Segment µ-255 Companding.
IEEE Trans. Commun., 1976

Statistical Analysis of a Differential Threshold Logic Circuit Configuration.
IEEE Trans. Computers, 1976

1975
Digital Multiplier Power Estimates.
IEEE Trans. Commun., 1975

1973
A Two's Complement Parallel Array Multiplication Algorithm.
IEEE Trans. Computers, 1973


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