James P. Norum

According to our database, James P. Norum authored at least 3 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.

Gregory Freeman, Paul Chang, E. R. Engbrecht, K. J. Giewont, David F. Hilscher, M. Lagus, Timothy J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik

IBM J. Res. Dev., 2015

2011

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.

Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello

IBM J. Res. Dev., 2011

2005

Embedded DRAM: Technology platform for the Blue Gene/L chip.

Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak

IBM J. Res. Dev., 2005