Shreesh Narasimha

According to our database1, Shreesh Narasimha authored at least 5 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges.
Microelectron. Reliab., 2015

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.
IBM J. Res. Dev., 2015

2011
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.
IBM J. Res. Dev., 2011

2007
Optimization of silicon technology for the IBM System z9.
IBM J. Res. Dev., 2007

2003
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.
IBM J. Res. Dev., 2003


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