Paul D. Agnello

According to our database, Paul D. Agnello authored at least 6 papers between 1995 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.

Gregory Freeman, Paul Chang, E. R. Engbrecht, K. J. Giewont, David F. Hilscher, M. Lagus, Timothy J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik

IBM J. Res. Dev., 2015

2012

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.

Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.

Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello

IBM J. Res. Dev., 2011

2007

Optimization of silicon technology for the IBM System z9.

Daniel J. Poindexter, Scott R. Stiffler, Philip T. Wu, Paul D. Agnello, Thomas Ivers, Shreesh Narasimha, Thomas B. Faure, Jed H. Rankin, David A. Grosch, Marc D. Knox, Daniel C. Edelstein, Mukesh Khare, Gary B. Bronner, Hyun-Jang Nam, Shahid A. Butt

IBM J. Res. Dev., 2007

2002

Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation.

Paul D. Agnello

IBM J. Res. Dev., 2002

1995

Silicides and local interconnections for high-performance VLSI applications.

Randy W. Mann, Larry A. Clevenger, Paul D. Agnello, Francis R. White

IBM J. Res. Dev., 1995