Paul C. Parries

According to our database1, Paul C. Parries authored at least 9 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs.
IBM J. Res. Dev., 2018

2015
Performance-optimized gate-first 22-nm SOI technology with embedded DRAM.
IBM J. Res. Dev., 2015

2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.
IBM J. Res. Dev., 2011

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Embedded DRAM: Technology platform for the Blue Gene/L chip.
IBM J. Res. Dev., 2005


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