Jannis Stoppe

According to our database1, Jannis Stoppe authored at least 22 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
A Whole World of Circuitry - Visualizing Integrated Circuits using Geo Information Systems.
Balt. J. Mod. Comput., 2021

2020
Automated Nonintrusive Analysis of Electronic System Level Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems.
Proceedings of the Dynamics in Logistics, 2018

2017
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2017

Effects of cell shapes on the routability of Digital Microfluidic Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Change impact analysis for hardware designs from natural language to system level.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

2015
Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications.
Sensors, 2015

Verification-Driven Design Across Abstraction Levels: A Case Study.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Automated feature localization for dynamically generated SystemC designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Validating SystemC Implementations Against Their Formal Specifications.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

2013
Data extraction from SystemC designs using debug symbols and the SystemC API.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Cone of Influence Analysis at the Electronic System Level Using Machine Learning.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2011
Skeleton comparisons: the junction neighbourhood histogram.
Proceedings of the 2011 ACM Symposium on Document Engineering, 2011

2010
Down to the bone: simplifying skeletons.
Proceedings of the 2010 ACM Symposium on Document Engineering, 2010


  Loading...