Nils Przigoda

Orcid: 0000-0001-8947-3282

According to our database1, Nils Przigoda authored at least 31 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Design Tasks and Their Complexity for Hybrid Level 3 of the European Train Control System.
CoRR, 2023

Coverage-Driven Test Automation for Highly-Configurable Railway Systems.
Proceedings of the 17th International Working Conference on Variability Modelling of Software-Intensive Systems, 2023

2022
Optimal Railway Routing Using Virtual Subsections.
Proceedings of the Reliability, Safety, and Security of Railway Systems. Modelling, Analysis, Verification, and Certification, 2022

2021
Towards Automatic Design and Verification for Level 3 of the European Train Control System.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018
Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of <i>modifies only</i> statements.
Comput. Lang. Syst. Struct., 2018

Generation and Validation of Frame Conditions in Formal Models.
Proceedings of the Model-Driven Engineering and Software Development, 2018

Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence.
Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers
Springer, ISBN: 978-3-319-72813-1, 2018

2017
SMT-based validation & verification of UML-OCL models.
PhD thesis, 2017

Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

2016
Analyzing Inconsistencies in UML/OCL Models.
J. Circuits Syst. Comput., 2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Ground setting properties for an efficient translation of OCL in SMT-based model finding.
Proceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems, 2016

Integrating an SMT-Based ModelFinder into USE.
Proceedings of the 13th Workshop on Model-Driven Engineering, 2016

Frame conditions in symbolic representations of UML/OCL models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Fault Detection in Parity Preserving Reversible Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Towards a model-based verification methodology for Complex Swarm Systems (Invited paper).
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses.
Proceedings of the 12th Workshop on Model-Driven Engineering, 2015

Checking concurrent behavior in UML/OCL models.
Proceedings of the 18th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2015

Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Leveraging the Analysis for Invariant Independence in Formal System Models.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Verification-Driven Design Across Abstraction Levels: A Case Study.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Contradiction Analysis for Inconsistent Formal Models.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

A generic representation of CCSL time constraints for UML/MARTE models.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits.
J. Multiple Valued Log. Soft Comput., 2013

A compact and efficient SAT encoding for quantum circuits.
Proceedings of the AFRICON 2013, Pointe aux Piments, Mauritius, September 9-12, 2013, 2013

2012
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Synthesis of reversible circuits with minimal lines for large functions.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012


  Loading...