Oliver Keszöcze

Orcid: 0000-0003-2033-6153

According to our database1, Oliver Keszöcze authored at least 49 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
Artificial intelligence for molecular communication.
it Inf. Technol., August, 2023

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations.
CoRR, 2023

2022
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Approximate Computing.
it Inf. Technol., 2022

Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains.
it Inf. Technol., 2022

Towards Clause Learning à la Carte through VarMonads.
CoRR, 2022

BDD-Based Error Metric Analysis, Computation and Optimization.
IEEE Access, 2022

Using Deep Learning to Demodulate Transmissions in Molecular Communication.
Proceedings of the 16th IEEE International Symposium on Medical Information and Communication Technology, 2022

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Efficient One-pass Synthesis for Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2021

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains.
CoRR, 2021

Aarith: an arbitrary precision number library.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021

Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
One-pass Synthesis for Digital Microfluidic Biochips: A Survey.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A fast BDD Minimization Framework for Approximate Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Probabilistic Error Propagation through Approximated Boolean Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Chatbot-based assertion generation from natural language specifications.
Proceedings of the 2019 Forum for Specification and Design Languages, 2019

2018
On the complexity of design tasks for Digital Microfluidic Biochips.
Microelectron. J., 2018

The complexity of error metrics.
Inf. Process. Lett., 2018

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Translating Between the Roots of the Identity in Quantum Computers.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017
Exact design of digital microfluidic biochips.
PhD thesis, 2017

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs.
J. Low Power Electron., 2017

Synthesis of optical circuits using binary decision diagrams.
Integr., 2017

Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exakter Entwurf digitaler mikrofluidischer Biochips.
Proceedings of the Ausgezeichnete Informatikdissertationen 2017, 2017

Effects of cell shapes on the routability of Digital Microfluidic Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Exact routing for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Embedding of Large Boolean Functions for Reversible Logic.
ACM J. Emerg. Technol. Comput. Syst., 2016

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Generating and checking control logic in the HDL-based design of reversible circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Synthesis of approximate coders for on-chip interconnects using reversible logic.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Scalable One-Pass Synthesis for Digital Microfluidic Biochips.
IEEE Des. Test, 2015

A General and Exact Routing Methodology for Digital Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Reverse BDD-based synthesis for splitter-free optical circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Logic for Cardinality Constraints (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Exact routing for digital microfluidic biochips with temporary blockages.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Exact One-pass Synthesis of Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Task-Driven Software Summarization.
Proceedings of the 2013 IEEE International Conference on Software Maintenance, 2013

2011
Determining the minimal number of lines for large reversible circuits.
Proceedings of the Design, Automation and Test in Europe, 2011


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