Javier Olivito

According to our database, Javier Olivito authored at least 7 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems.

Adrián Alcolea Morena, Javier Olivito, Javier Resano, Hortensia Mecha

IEEE Trans. Very Large Scale Integr. Syst., 2020

2018

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.

Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano

IET Comput. Digit. Tech., 2018

2017

Accelerating Board Games Through Hardware/Software Codesign.

Javier Olivito, Javier Resano, José Luis Briz

IEEE Trans. Comput. Intell. AI Games, 2017

2015

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors.

Javier Olivito, Ruben Gran, Javier Resano, Carlos González, Enrique F. Torres

Microprocess. Microsystems, 2015

2014

An improved FPGA-based specific processor for Blokus Duo.

Javier Olivito, Alberto Delmas, Javier Resano

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013

An FPGA-based specific processor for Blokus Duo.

Javier Olivito, Carlos González, Javier Resano

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2010

FPGA implementation of a strong Reversi player.

Javier Olivito, Carlos González, Javier Resano

Proceedings of the International Conference on Field-Programmable Technology, 2010