Ruben Gran Tejero

According to our database1, Ruben Gran Tejero authored at least 21 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
The Journal of Supercomputing, 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
The Journal of Supercomputing, 2019

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL.
The Journal of Supercomputing, 2019

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.
J. Syst. Archit., 2019

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018

Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
Proceedings of the Parallel Computing is Everywhere, 2017

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.
IEEE Trans. VLSI Syst., 2016

Mapping Streaming Applications on Commodity Multi-CPU and GPU On-Chip Processors.
IEEE Trans. Parallel Distrib. Syst., 2016

ACDC: Small, Predictable and High-Performance Data Cache.
ACM Trans. Embedded Comput. Syst., 2015

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors.
Microprocess. Microsystems, 2015

A predictable hardware to exploit temporal reuse in real-time and embedded systems.
J. Syst. Archit., 2015

Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips.
Proceedings of the International Conference on Computational Science, 2015

Evaluation of a Feature Tracking Vision Application on a Heterogeneous Chip.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Directive-Based Compilers for GPUs.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems.
J. Syst. Archit., 2013

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
TACO, 2012

A Small and Effective Data Cache for Real-Time Multitasking Systems.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

On reducing misspeculations in a pipelined scheduler.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

An Enhancement for a Scheduling Logic Pipelined over two Cycles .
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006