Ruben Gran Tejero

According to our database, Ruben Gran Tejero authored at least 35 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators.

Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Lightweight asynchronous scheduling in heterogeneous reconfigurable systems.

Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo

J. Syst. Archit., 2022

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators.

Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni

J. Syst. Archit., 2022

A cross-platform OpenVX library for FPGA accelerators.

Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Diana Göhringer

J. Syst. Archit., 2022

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter.

Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021

Analytical Model for Memory-Centric High Level Synthesis-Generated Applications.

Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia

IEEE Trans. Computers, 2021

A generic framework to integrate data caches in the WCET analysis of real-time systems.

Juan Segarra, Ruben Gran Tejero, Víctor Viñals

J. Syst. Archit., 2021

A learning experience toward the understanding of abstraction-level interactions in parallel applications.

Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez

J. Parallel Distributed Comput., 2021

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.

Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia

CoRR, 2021

2020

Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.

Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez

J. Supercomput., 2020

Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.

Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia

CoRR, 2020

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.

Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero

IEEE Access, 2020

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches.

Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera

IEEE Access, 2020

An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.

Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.

José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran

J. Supercomput., 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.

José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran

J. Supercomput., 2019

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL.

Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, José Luis Bosque

J. Supercomput., 2019

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.

Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez

J. Syst. Archit., 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals

Proceedings of the Workshop on Computer Architecture Education, 2019

2018

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.

José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia

CoRR, 2018

Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems.

Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia

Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

2017

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.

José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia

Proceedings of the Parallel Computing is Everywhere, 2017

2016

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.

Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, Javier Resano

IEEE Trans. Very Large Scale Integr. Syst., 2016

Mapping Streaming Applications on Commodity Multi-CPU and GPU On-Chip Processors.

Antonio Vilches, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, María Jesús Garzarán

IEEE Trans. Parallel Distributed Syst., 2016

2015

ACDC: Small, Predictable and High-Performance Data Cache.

Juan Segarra, Clemente Rodríguez, Ruben Gran, Luis C. Aparicio, Víctor Viñals

ACM Trans. Embed. Comput. Syst., 2015

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors.

Javier Olivito, Ruben Gran, Javier Resano, Carlos González, Enrique F. Torres

Microprocess. Microsystems, 2015

A predictable hardware to exploit temporal reuse in real-time and embedded systems.

Ruben Gran, Juan Segarra, A. Pedro-Zapater, Luis C. Aparicio, Víctor Viñals, Clemente Rodríguez

J. Syst. Archit., 2015

Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips.

Antonio Vilches, Rafael Asenjo, Angeles G. Navarro, Francisco Corbera, Ruben Gran Tejero, María Jesús Garzarán

Proceedings of the International Conference on Computational Science, 2015

2014

Evaluation of a Feature Tracking Vision Application on a Heterogeneous Chip.

Ruben Gran, August Shi, Ehsan Totoni, María Jesús Garzarán

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Directive-Based Compilers for GPUs.

Swapnil Ghike, Ruben Gran, María Jesús Garzarán, David A. Padua

Proceedings of the Languages and Compilers for Parallel Computing, 2014

2013

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems.

Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals

J. Syst. Archit., 2013

2012

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.

Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería

ACM Trans. Archit. Code Optim., 2012

A Small and Effective Data Cache for Real-Time Multitasking Systems.

Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals

Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

2009

On reducing misspeculations in a pipelined scheduler.

Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2006

An Enhancement for a Scheduling Logic Pipelined over two Cycles .

Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006