Javier Resano

Orcid: 0000-0002-7532-2720

According to our database1, Javier Resano authored at least 42 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Bayesian Neural Networks to Analyze Hyperspectral Datasets Using Uncertainty Metrics.
IEEE Trans. Geosci. Remote. Sens., 2022

GPU-Friendly Neural Networks for Remote Sensing Scene Classification.
IEEE Geosci. Remote. Sens. Lett., 2022

2020
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Inference in Supervised Spectral Classifiers for On-Board Hyperspectral Imaging: An Overview.
Remote. Sens., 2020

2019

2018
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
IET Comput. Digit. Tech., 2018

2017
Accelerating Board Games Through Hardware/Software Codesign.
IEEE Trans. Comput. Intell. AI Games, 2017

2016
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors.
Microprocess. Microsystems, 2015

2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems.
ACM Trans. Embed. Comput. Syst., 2014

An improved FPGA-based specific processor for Blokus Duo.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends.
Proc. IEEE, 2013

Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing.
Integr., 2013

An FPGA-based specific processor for Blokus Duo.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis.
IEEE Trans. Geosci. Remote. Sens., 2012

FPGA Implementation of Abundance Estimation for Spectral Unmixing of Hyperspectral Data Using the Image Space Reconstruction Algorithm.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2012

2011
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Mini workshop - Real World Engineering Projects: Discovery-based curriculum modules for first-year students.
Proceedings of the 2011 Frontiers in Education Conference, 2011

2010
A task graph execution manager for reconfigurable multi-tasking systems.
Microprocess. Microsystems, 2010

FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis.
EURASIP J. Adv. Signal Process., 2010

FPGA implementation of a strong Reversi player.
Proceedings of the International Conference on Field-Programmable Technology, 2010

FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
FPGA support for satellite computations of hyper spectral images.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Efficiently scheduling runtime reconfigurations.
ACM Trans. Design Autom. Electr. Syst., 2008

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Memory hierarchy for high-performance and energyaware reconfigurable systems.
IET Comput. Digit. Tech., 2007

HW implementation of an execution manager for reconfigurable systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Reducing the reconfiguration overhead: a survey of techniques.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Dual Cache for Performance and Energy Aware Reconfigurable HW.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
A Reconfiguration Manager for Dynamically Reconfigurable Hardware.
IEEE Des. Test Comput., 2005

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware.
Proceedings of the 2005 Design, 2005

2004
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocess. Microsystems, 2004

A Specific Scheduling Flow for Dynamically Reconfigurable Hardware.
Proceedings of the Field Programmable Logic and Application, 2004

Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware.
Proceedings of the 41th Design Automation Conference, 2004

2003
Analyzing communication overheads during hardware/software partitioning.
Microelectron. J., 2003

A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
Proceedings of the Integrated Circuit and System Design, 2003

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003


  Loading...