José Luis Briz

Orcid: 0000-0001-5940-9837

Affiliations:
  • University of Zaragoza, Spain


According to our database1, José Luis Briz authored at least 18 papers between 1994 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs.
IEEE Robotics Autom. Lett., 2022

2021
Maximizing Utilization and Minimizing Migration in Thermal-Aware Energy-Efficient Real-Time Multiprocessor Scheduling.
IEEE Access, 2021

2019
Thermal-aware Real-time Scheduling Using Timed Continuous Petri Nets.
ACM Trans. Embed. Comput. Syst., 2019

Energy-efficient thermal-aware multiprocessor scheduling for real-time tasks using TCPN.
Discret. Event Dyn. Syst., 2019

A Flexible Framework for Real-Time Thermal-Aware Schedulers using Timed Continuous Petri Nets.
Computación y Sistemas, 2019


2018
GPU NTC Process Variation Compensation With Voltage Stacking.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Accelerating Board Games Through Hardware/Software Codesign.
IEEE Trans. Comput. Intell. AI Games, 2017

2016
Managing Mismatches in Voltage Stacking with CoreUnfolding.
ACM Trans. Archit. Code Optim., 2016

On-line scheduling in multiprocessor systems based on continuous control using Timed Continuous Petri Nets.
Proceedings of the 13th International Workshop on Discrete Event Systems, 2016

2013
An energy efficient GPGPU memory hierarchy with tiny incoherent caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2011
Multi-level Adaptive Prefetching based on Performance Gradient Tracking.
J. Instr. Level Parallelism, 2011

2008
Low-Cost Adaptive Data Prefetching.
Proceedings of the Euro-Par 2008, 2008

2007
Data prefetching in a cache hierarchy with high bandwidth and capacity.
SIGARCH Comput. Archit. News, 2007

2006
Software Demand, Hardware Supply.
IEEE Micro, 2006

2001
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

1998
Characterization and Improvement of Load/Store Cache-based Prefetching.
Proceedings of the 12th international conference on Supercomputing, 1998

1994
Implementation of Weighted Place/Transition Nets Based on Linear Enabling Functions.
Proceedings of the Application and Theory of Petri Nets 1994, 1994


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