Juan Antonio Clemente

Orcid: 0000-0002-7855-1051

According to our database1, Juan Antonio Clemente authored at least 22 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles.
Microprocess. Microsystems, February, 2023

2022
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories.
IEEE Access, 2022

2021
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020
Impact of Ground-Level Enhancement (GLE) Solar Events on Soft Error Rate for Avionics.
IEEE Trans. Aerosp. Electron. Syst., 2020

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets.
Reliab. Eng. Syst. Saf., 2020

2018
A decomposition-based reliability and makespan optimization technique for hardware task graphs.
Reliab. Eng. Syst. Saf., 2018

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
IET Comput. Digit. Tech., 2018

2017
Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms.
IEEE Trans. Aerosp. Electron. Syst., 2017

2016
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs.
Neurocomputing, 2016

2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.
ACM Trans. Reconfigurable Technol. Syst., 2014

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems.
ACM Trans. Embed. Comput. Syst., 2014

2011
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
A task graph execution manager for reconfigurable multi-tasking systems.
Microprocess. Microsystems, 2010

2008
Efficiently scheduling runtime reconfigurations.
ACM Trans. Design Autom. Electr. Syst., 2008

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
HW implementation of an execution manager for reconfigurable systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007


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