Jayaprakash Balachandran

According to our database, Jayaprakash Balachandran authored at least 3 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Power Integrity Analysis for Interoperability of BoW Chiplet Interfaces.

Ishan Mishra, Jayaprakash Balachandran, Wen-Sin Liew, Elad Alon, Srinivas Venkataraman, Shalabh Gupta

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2013

An Intelligent RAM with Serial I/Os.

Bendik Kleveland, Michael John Miller, Ronald B. David, Jay Patel, Rajesh Chopra, Dipak K. Sikdar, Jeff Kumala, Socrates D. Vamvakos, Mike Morrison, Ming Liu, Jayaprakash Balachandran

IEEE Micro, 2013

2012

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.

Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung

Proceedings of the 38th European Solid-State Circuit conference, 2012