Haidang Lin

According to our database, Haidang Lin authored at least 6 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.

Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai

IEEE J. Solid State Circuits, 2021

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.

Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai

IEEE J. Solid State Circuits, 2021

2020

A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET.

Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.

Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2014

A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop.

Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.

Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung

Proceedings of the 38th European Solid-State Circuit conference, 2012