Shaishav Desai

According to our database1, Shaishav Desai authored at least 11 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021

2020

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2014
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012


2009
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007



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