Jayasanker Jayabalan

According to our database, Jayasanker Jayabalan authored at least 4 papers between 2002 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning.

Zheng Wang, Yi Chen, Aakash Patil, Jayasanker Jayabalan, Xueyong Zhang, Chip-Hong Chang, Arindam Basu

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2006

Multi-Gigahertz Testing of Wafer-Level Packaged Devices.

A. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru

Proceedings of the 2006 IEEE International Test Conference, 2006

2003

PLL Based High Speed Functional Testing.

Jayasanker Jayabalan, Kiang Goh Chee, Ban-Leong Ooi, Mook Seng Leong, Mahadevan K. Iyer, Andrew A. O. Tay

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Integration of SRAM Redundancy into Production Test.

Jayasanker Jayabalan, Juraj Povazanec

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002