Juraj Povazanec

According to our database, Juraj Povazanec authored at least 10 papers between 1996 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

Integration of SRAM Redundancy into Production Test.

Jayasanker Jayabalan, Juraj Povazanec

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

A New Control Circuit for Asynchronous Micropipelines.

Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan

IEEE Trans. Computers, 2001

Asynchronous cross-pipelined multiplier.

Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan

IEEE J. Solid State Circuits, 2001

A single chip terminal solution for high-end telephone applications.

Vinod Nair, Martin Erdmann, Shridhar Mubaraq Mishra, Juraj Povazanec, Amit Shaligram, Chun Feng Hu

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1999

Pipelined Dataflow Architecture of a Small Processor.

Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998

Asynchronous logic in bit-serial arithmetic.

Juraj Povazanec, Chiu-Sing Choy, Cheong-Fat Chan

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Useful Micropipeline Architecture to Implement DSP Algorithms.

Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-Fat Chan

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

Fault and test-process modelling for integrated circuits.

Juraj Povazanec, Vladislav Musil

J. Syst. Archit., 1997

1996

Neural network based system for testing and diagnostics of analogue integrated circuits.

Jirí Kaderka, Vladislav Musil, Juraj Povazanec, Petr Simek

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Test-Process Simulation with Neural Network Evaluation.

Juraj Povazanec, Jirí Kaderka, Vladislav Musil, Petr Simek

Proceedings of the Modelling and Simulation, 1996