Jean-Luc Beuchat

Orcid: 0000-0002-7161-4005

According to our database1, Jean-Luc Beuchat authored at least 41 papers between 1998 and 2023.

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Bibliography

2023
A Digital Identity in the Hands of Swiss Citizens.
IACR Cryptol. ePrint Arch., 2023

2017
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl.
J. Parallel Distributed Comput., 2017

2016
Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures.
IEEE ACM Trans. Comput. Biol. Bioinform., 2016

2013
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA.
IACR Cryptol. ePrint Arch., 2013

2012
Compact Implementation of Threefish and Skein on FPGA.
IACR Cryptol. ePrint Arch., 2012

2011
Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves.
IEEE Trans. Computers, 2011

A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO.
J. Cryptogr. Eng., 2011

2010
A Compact FPGA Implementation of the SHA-3 Candidate ECHO.
IACR Cryptol. ePrint Arch., 2010

Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA.
IACR Cryptol. ePrint Arch., 2010

High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves.
IACR Cryptol. ePrint Arch., 2010

Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves.
IACR Cryptol. ePrint Arch., 2010

FPGA and ASIC implementations of the eta<sub>T</sub> pairing in characteristic three.
Comput. Electr. Eng., 2010

2009
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves.
IACR Cryptol. ePrint Arch., 2009

Fast Architectures for the eta<sub>T</sub> Pairing over Small-Characteristic Supersingular Elliptic Curves.
IACR Cryptol. ePrint Arch., 2009

Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.
IACR Cryptol. ePrint Arch., 2009

2008
Automatic Generation of Modular Multipliers for FPGA Applications.
IEEE Trans. Computers, 2008

Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three.
IEEE Trans. Computers, 2008

A Pipelined Karatsuba-Ofman Multiplier over GF(3<sup>97</sup>) Amenable for Pairing Computation.
IACR Cryptol. ePrint Arch., 2008

A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F<sub>2<sup>m</sup></sub> and F<sub>3<sup>m</sup></sub>.
IACR Cryptol. ePrint Arch., 2008

2007
A Refined Algorithm for the eta<sub>T</sub> Pairing Calculation in Characteristic Three.
IACR Cryptol. ePrint Arch., 2007

A Coprocessor for the Final Exponentiation of the eta<sub>T</sub> Pairing in Characteristic Three.
IACR Cryptol. ePrint Arch., 2007

Algorithms and Arithmetic Operators for Computing the eta<sub>T</sub> Pairing in Characteristic Three.
IACR Cryptol. ePrint Arch., 2007

Arithmetic Operators for Pairing-Based Cryptography.
IACR Cryptol. ePrint Arch., 2007

Further Comments on "Residue-to-Binary Converters Based on New Chinese Remainder Theorems"
CoRR, 2007

A Coprocessor for the Final Exponentiation of the <i>eta</i> <sub> <i>T</i> </sub> Pairing in Characteristic Three.
Proceedings of the Arithmetic of Finite Fields, First International Workshop, 2007

An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

Multiplication over F<sub>p<sup>m</sup></sub> on FPGA: A Survey.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
An Algorithm for the η<sub>T</sub> Pairing Calculation in Characteristic Three and its Hardware Implementation.
IACR Cryptol. ePrint Arch., 2006

2005
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA.
Tech. Sci. Informatiques, 2004

2003
Some Modular Adders and Multipliers for Field Programmable Gate Arrays.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

FPGA Implementations of the RC6 Block Cipher.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Approches matérielles et logicielles de l'algorithme de chiffrement IDEA.
Tech. Sci. Informatiques, 2002

Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.
Proceedings of the Field-Programmable Logic and Applications, 2002

2000
Von Neumann's 29-state cellular automaton: a hardware implementation.
IEEE Trans. Educ., 2000

1999
Static and Dynamic Configurable Systems.
IEEE Trans. Computers, 1999

Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations.
Proceedings of the Engineering Applications of Bio-Inspired Artificial Neural Networks, 1999

An On-Line Arithmetic-Based Reconfigurable Neuroprocessor.
Proceedings of the Parallel and Distributed Processing, 1999

1998
Hardware Reconfigurable Neural Networks.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

RENCO: A Reconfigurable Network Computer.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998


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