Mehran Mozaffari Kermani

Orcid: 0000-0003-4513-3109

According to our database1, Mehran Mozaffari Kermani authored at least 126 papers between 2006 and 2024.

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Bibliography

2024
Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Hardware Constructions for Error Detection in WG-29 Stream Cipher Benchmarked on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

Cryptographic Engineering a Fast and Efficient SIKE in FPGA.
ACM Trans. Embed. Comput. Syst., March, 2024

Efficient Algorithm Level Error Detection for Number-Theoretic Transform Assessed on FPGAs.
CoRR, 2024

Efficient Fault Detection Architectures for Modular Exponentiation Targeting Cryptographic Applications Benchmarked on FPGAs.
CoRR, 2024

Fully Hybrid TLSv1.3 in WolfSSL on Cortex-M4.
Proceedings of the Applied Cryptography and Network Security Workshops, 2024

2023
Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic Transform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes.
IEEE Trans. Reliab., 2023

Error Detection Schemes Assessed on FPGA for Multipliers in Lattice-Based Key Encapsulation Mechanisms in Post-Quantum Cryptography.
IEEE Trans. Emerg. Top. Comput., 2023

Time-Efficient Finite Field Microarchitecture Design for Curve448 and Ed448 on Cortex-M4.
IACR Cryptol. ePrint Arch., 2023

Envisioning the Future of Cyber Security in Post-Quantum Era: A Survey on PQ Standardization, Applications, Challenges and Opportunities.
CoRR, 2023

ChatGPT vs. Lightweight Security: First Work Implementing the NIST Cryptographic Standard ASCON.
CoRR, 2023

Algorithmic Security is Insufficient: A Comprehensive Survey on Implementation Attacks Haunting Post-Quantum Security.
CoRR, 2023

A Comprehensive Survey on the Implementations, Attacks, and Countermeasures of the Current NIST Lightweight Cryptography Standard.
CoRR, 2023

Engaged Student Learning with Gamified Labs: A New Approach for Hardware Security Education.
Proceedings of the IEEE International Conference on Teaching, 2023

Reliable Code-Based Post-Quantum Cryptographic Algorithms through Fault Detection on FPGA.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

Highly Optimized Curve448 and Ed448 design in wolfSSL and Side-Channel Evaluation on Cortex-M4.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2023

2022
Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Hardware Constructions for Error Detection in Lightweight Welch-Gong (WG)-Oriented Streamcipher WAGE Benchmarked on FPGA.
IEEE Trans. Emerg. Top. Comput., 2022

Hardware Constructions for Lightweight Cryptographic Block Cipher QARMA With Error Detection Mechanisms.
IEEE Trans. Emerg. Top. Comput., 2022

Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Accelerated RISC-V for Post-Quantum SIKE.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

High-Performance FPGA Accelerator for SIKE.
IEEE Trans. Computers, 2022

Time-Optimal Design of Finite Field Arithmetic for SIKE on Cortex-M4.
Proceedings of the Information Security Applications - 23rd International Conference, 2022

CRC-Oriented Error Detection Architectures of Post-quantum Cryptography Niederreiter Key Generator on FPGA.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

Improving Student Learning in Hardware Security: Project Vision, Overview, and Experiences.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Efficient and Side-Channel Resistant Design of High-Security Ed448 on ARM Cortex-M4.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Cryptographic Accelerators for Digital Signature Based on Ed25519.
IEEE Trans. Very Large Scale Integr. Syst., 2021

CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2021

Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in $\boldsymbol{\frac{\mathbb{Z}/p\mathbb{Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC.
IEEE Trans. Reliab., 2021

Fault Detection Architectures for Inverted Binary Ring-LWE Construction Benchmarked on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Area-Time Efficient Hardware Architecture for Signature Based on Ed448.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Instruction-Set Accelerated Implementation of CRYSTALS-Kyber.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Fast Strategies for the Implementation of SIKE Round 3 on ARM Cortex-M4.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Kyber on ARM64: Compact Implementations of Kyber on 64-bit ARM Cortex-A Processors.
IACR Cryptol. ePrint Arch., 2021

High-Speed NTT-based Polynomial Multiplication Accelerator for CRYSTALS-Kyber Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2021

Accelerated RISC-V for Post-Quantum SIKE.
IACR Cryptol. ePrint Arch., 2021

Compressed SIKE Round 3 on ARM Cortex-M4.
IACR Cryptol. ePrint Arch., 2021

A Monolithic Hardware Implementation of Kyber: Comparing Apples to Apples in PQC Candidates.
Proceedings of the Progress in Cryptology - LATINCRYPT 2021, 2021

High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography.
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

Accelerated RISC-V for SIKE.
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021

2020
SIKE'd Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation.
IEEE Trans. Circuits Syst., 2020

Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519.
IACR Cryptol. ePrint Arch., 2020

Optimized Architectures for Elliptic Curve Cryptography over Curve448.
IACR Cryptol. ePrint Arch., 2020

Efficient and Fast Hardware Architectures for SIKE Round 2 on FPGA.
IACR Cryptol. ePrint Arch., 2020

Efficient Hardware Implementations for Elliptic Curve Cryptography over Curve448.
Proceedings of the Progress in Cryptology - INDOCRYPT 2020, 2020

Highly Optimized Montgomery Multiplier for SIKE Primes on FPGA.
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Reliable Architecture-Oblivious Error Detection Schemes for Secure Cryptographic GCM Structures.
IEEE Trans. Reliab., 2019

Supersingular Isogeny Diffie-Hellman Key Exchange on 64-Bit ARM.
IEEE Trans. Dependable Secur. Comput., 2019

ARMv8 SIKE: Optimized Supersingular Isogeny Key Encapsulation on ARMv8 Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

SIKE'd Up: Fast and Secure Hardware Architectures for Supersingular Isogeny Key Encapsulation.
IACR Cryptol. ePrint Arch., 2019

Towards Optimized and Constant-Time CSIDH on Embedded Devices.
IACR Cryptol. ePrint Arch., 2019

Optimized Supersingular Isogeny Key Encapsulation on ARMv8 Processors.
IACR Cryptol. ePrint Arch., 2019

High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Optimized Algorithms and Architectures for Montgomery Multiplication for Post-quantum Cryptography.
Proceedings of the Cryptology and Network Security - 18th International Conference, 2019

2018
Efficient and Reliable Error Detection Architectures of Hash-Counter-Hash Tweakable Enciphering Schemes.
ACM Trans. Embed. Comput. Syst., 2018

Reliable Inversion in GF(2<sup>8</sup>) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography.
IEEE Trans. Computers, 2018

Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue.
CoRR, 2018

Towards Lightweight Error Detection Schemes for Implementations of MixColumns in Lightweight Cryptography.
CoRR, 2018

NEON SIKE: Supersingular Isogeny Key Encapsulation on ARMv7.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Lightweight Error Detection Architectures through Swapping the Shares for a Subset of S-boxes.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Design-for-Error-Detection in Implementations of Cryptographic Nonlinear Substitution Boxes Benchmarked on ASIC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Reliable hardware architectures for efficient secure hash functions ECHO and fugue.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Comparative realization of error detection schemes for implementations of mixcolumns in lightweight cryptography.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fault Detection Architectures for Post-Quantum Cryptographic Stateless Hash-Based Secure Signatures Benchmarked on ASIC.
ACM Trans. Embed. Comput. Syst., 2017

Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA.
ACM Trans. Embed. Comput. Syst., 2017

Emerging Embedded and Cyber Physical System Security Challenges and Innovations.
IEEE Trans. Dependable Secur. Comput., 2017

Reliable Hardware Architectures of the CORDIC Algorithm With a Fixed Angle of Rotations.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Efficient Post-Quantum Undeniable Signature on 64-Bit ARM.
Proceedings of the Selected Areas in Cryptography - SAC 2017, 2017

2016
Guest Editorial: Introduction to the Special Issue on Emerging Security Trends for Deeply-Embedded Computing Systems.
IEEE Trans. Emerg. Top. Comput., 2016

Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures.
IEEE ACM Trans. Comput. Biol. Bioinform., 2016

Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman Key Exchange on FPGA.
IACR Cryptol. ePrint Arch., 2016

On Fast Calculation of Addition Chains for Isogeny-Based Cryptography.
IACR Cryptol. ePrint Arch., 2016

NEON-SIDH: Effi cient Implementation of Supersingular Isogeny Diffi e-Hellman Key-Exchange Protocol on ARM.
IACR Cryptol. ePrint Arch., 2016

Efficient error detection architectures for CORDIC through recomputing with encoded operands.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Lightweight hardware architectures for fault diagnosis schemes of efficiently-maskable cryptographic substitution boxes.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Fault diagnosis schemes for secure lightweight cryptographic block cipher RECTANGLE benchmarked on FPGA.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

NEON-SIDH: Efficient Implementation of Supersingular Isogeny Diffie-Hellman Key Exchange Protocol on ARM.
Proceedings of the Cryptology and Network Security - 15th International Conference, 2016

2015
Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Energy-Efficient Long-term Continuous Personal Health Monitoring.
IEEE Trans. Multi Scale Comput. Syst., 2015

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.
IEEE J. Biomed. Health Informatics, 2015

Reliable Radix-4 Complex Division for Fault-Sensitive Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Secure and Efficient Architectures for Single Exponentiations in Finite Fields Suitable for High-Performance Cryptographic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Low-Resource and Fast Binary Edwards Curves Cryptography.
Proceedings of the Progress in Cryptology - INDOCRYPT 2015, 2015

Reliable hash trees for post-quantum stateless cryptographic hash-based signatures.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Generalized parallel CRC computation on FPGA.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2014
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2014

Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely Constrained Secure Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Computers, 2014

Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems.
IEEE Embed. Syst. Lett., 2014

2013
Efficient Fault Diagnosis Schemes for Reliable Lightweight Cryptographic ISO/IEC Standard CLEFIA Benchmarked on ASIC and FPGA.
IEEE Trans. Ind. Electron., 2013

Energy-efficient and Secure Sensor Data Transmission Using Encompression.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Emerging Frontiers in Embedded Security.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM.
IEEE Trans. Computers, 2012

2011
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box.
IEEE Trans. Computers, 2011

A High-Performance Fault Diagnosis Approach for the AES SubBytes Utilizing Mixed Bases.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard.
IEEE Trans. Computers, 2010

2009
Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard.
J. Electron. Test., 2009

A low-cost S-box for the Advanced Encryption Standard using normal basis.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

2008
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

2007
A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

2006
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Parity Prediction of S-Box for AES.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006


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