Arnaud Tisserand

Orcid: 0000-0001-7042-3541

According to our database1, Arnaud Tisserand authored at least 65 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

2022
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS.
IEEE Trans. Computers, 2022

Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2019
Generation of Finely-Pipelined GF(<i>P</i>P) Multipliers for Flexible Curve Based Cryptography on FPGAs.
IEEE Trans. Computers, 2019

FPGA Implementation and Comparison of Protections Against SCAs for RLWE.
Proceedings of the Progress in Cryptology - INDOCRYPT 2019, 2019

Evaluation of variable bit-width units in a RISC-V processor for approximate computing.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.
IEEE Trans. Computers, 2018

Computation of 2D 8×8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding.
IEEE Trans. Computers, 2018

Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Microcontroller Implementation of Simultaneous Protections Against Observation and Perturbation Attacks for ECC.
Proceedings of the 15th International Joint Conference on e-Business and Telecommunications, 2018

2017
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm.
ACM Trans. Embed. Comput. Syst., 2017

Introduction to the Special Issue on Computer Arithmetic.
IEEE Trans. Computers, 2017

Architecture level Optimizations for Kummer based HECC on FPGAs.
IACR Cryptol. ePrint Arch., 2017

An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Hyper-threaded multiplier for HECC.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Binary-Ternary Plus-Minus Modular Inversion in RNS.
IEEE Trans. Computers, 2016

Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Hybrid Position-Residues Number System.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
Improving Modular Inversion in RNS using the Plus-Minus Method.
IACR Cryptol. ePrint Arch., 2015

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier.
IEEE Embed. Syst. Lett., 2015

Exploration of polynomial multiplication algorithms for homomorphic encryption schemes.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m).
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Fast and Secure Finite Field Multipliers.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Robust sub-powered asynchronous logic.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

RNS modular multiplication through reduced base extensions.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Introduction.
Tech. Sci. Informatiques, 2013

On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012
$\textrm{GF}(2^m)$ Finite-Field Multipliers with Reduced Activity Variations.
Proceedings of the Arithmetic of Finite Fields - 4th International Workshop, 2012

Analysis of GF (2233) multipliers regarding elliptic curve cryptosystem applications.
Proceedings of the 11th IFAC Conference on Programmable Devices and Embedded Systems, 2012

2011
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Multiplication in GF(2m): Area and time dependency/efficiency/complexity analysis.
Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

Étude et conception d'opérateurs arithmétiques. (Study and design of arithmetic operators).
, 2010

2009
Comparison of Modular Arithmetic Algorithms on GPUs.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Power Consumption of GPUs from a Software Perspective.
Proceedings of the Computational Science, 2009

2008
Optimisation d'opérateurs arithmétiques matériels à base d'approximations polynomiales.
Tech. Sci. Informatiques, 2008

Error Detection for Borrow-Save Adders Dedicated to ECC Unit.
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

Fast and accurate activity evaluation in multipliers.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007
Chronique : Introduction aux représentations des nombres et opérateurs arithmétiques à basse consommation d'énergie.
Tech. Sci. Informatiques, 2007

Multi-mode operator for SHA-2 hash functions.
J. Syst. Archit., 2007

Comparison of Simple Power Analysis Attack Resistant Algorithms for an Elliptic Curve Cryptosystem.
J. Comput., 2007

High-performance hardware operators for polynomial evaluation.
Int. J. High Perform. Syst. Archit., 2007

SPA resistant elliptic curve cryptosystem using addition chains.
Int. J. High Perform. Syst. Archit., 2007

2006
Computing machine-efficient polynomial approximations.
ACM Trans. Math. Softw., 2006

Carry Prediction and Selection for Truncated Multiplication.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Hardware Operator for Simultaneous Sine and Cosine Evaluation.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
Multipartite Table Methods.
IEEE Trans. Computers, 2005

Some Optimizations of Hardware Multiplication by Constant Matrices.
IEEE Trans. Computers, 2005

Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Division by Constant for the ST100 DSP Microprocessor.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA.
Tech. Sci. Informatiques, 2004

2002
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Some Improvements on Multipartite Table Methods .
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers.
IEEE Trans. Computers, 2000

1999
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998
Semi-Logarithmic Number Systems.
IEEE Trans. Computers, 1998

Toward Correctly Rounded Transcendentals.
IEEE Trans. Computers, 1998

Field Programmable Processor Arrays.
Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

1997
Adéquation arithmétique architecture, problèmes et étude de cas. (Arithmetic architecture adequacy, problems and case study).
PhD thesis, 1997

FPGA implementation of real-time digital controllers using on-line arithmetic.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Towards Correctly Rounded Transcendentals.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997


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