Jeffrey A. Davis

According to our database1, Jeffrey A. Davis authored at least 26 papers between 2000 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2007

IntSim: A CAD tool for optimization of multilevel interconnect networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A priori prediction of tightly clustered connections based on heuristic classification trees.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

2005
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst., 2005

Optimization of throughput performance for low-power VLSI interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Designing for signal integrity in wave-pipelined SOC global interconnects.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Maximum Multiplicity Distributions for Length Prediction Driven Placement.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003
Maximum multiplicity distributions (MMD).
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Voltage scaling and repeater insertion for high-throughput low-power interconnects.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Interconnect opportunities for gigascale integration.
IBM J. Res. Dev., 2002

A physical model for the transient response of capacitively loaded distributed rlc interconnects.
Proceedings of the 39th Design Automation Conference, 2002

2001
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst., 2001

Impact of three-dimensional architectures on interconnects in gigascale integration.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2000

A compact physical via blockage model.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Prediction of interconnect fan-out distribution using Rent's rule.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000


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