James D. Meindl
Affiliations:- Georgia Institute of Technology, Atlanta GA, USA
According to our database1,
James D. Meindl
authored at least 59 papers
between 1986 and 2010.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1968, "For leadership and contributions in the field of microelectronic and integrated circuitry.".
Timeline
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Online presence:
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on id.loc.gov
On csauthors.net:
Bibliography
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.
Proceedings of the 44th Design Automation Conference, 2007
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects.
Proceedings of the 2006 IEEE International Test Conference, 2006
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration.
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
A physical model for the transient response of capacitively loaded distributed rlc interconnects.
Proceedings of the 39th Design Automation Conference, 2002
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
IEEE Trans. Computers, 2001
Proc. IEEE, 2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Impact of within-die parameter fluctuations on future maximum clock frequency distributions.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE J. Solid State Circuits, 2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI).
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
1994
IEEE J. Solid State Circuits, February, 1994
1991
Proceedings of the Proceedings Supercomputing '91, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1986