Chirag S. Patel

According to our database1, Chirag S. Patel authored at least 21 papers between 1997 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
Downlink Transmit Power Calibration for Enterprise Femtocells.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

Downlink interference management techniques for residential femtocells.
Proceedings of the IEEE 22nd International Symposium on Personal, 2011

2009
System design of CDMA2000 femtocells.
IEEE Commun. Mag., 2009

2008
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections.
IBM J. Res. Dev., 2008

Three-dimensional silicon integration.
IBM J. Res. Dev., 2008

3D chip stacking with C4 technology.
IBM J. Res. Dev., 2008

Field Results on MIMO Performance in UMB Systems.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

2007
Channel Estimation for Amplify and Forward Relay Based Cooperation Diversity Systems.
IEEE Trans. Wirel. Commun., 2007

2006
Wireless Channel Modeling, Simulation, and Estimation.
PhD thesis, 2006

Statistical properties of amplify and forward relay fading channels.
IEEE Trans. Veh. Technol., 2006

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias.
IEEE J. Solid State Circuits, 2006

Handoff performance analysis for 1xEV-DO Rev. A systems.
Proceedings of IEEE International Conference on Communications, 2006

Silicon carrier for computer systems.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Simulation of Rayleigh-faded mobile-to-mobile communication channels.
IEEE Trans. Commun., 2005

Comparative analysis of statistical models for the simulation of Rayleigh faded cellular channels.
IEEE Trans. Commun., 2005

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection.
IBM J. Res. Dev., 2005

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Analysis of OFDM/MC-CDMA under channel estimation and jamming.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004

2002
Interconnect opportunities for gigascale integration.
IBM J. Res. Dev., 2002

1997
Power/Performance Trade-offs for Direct Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

Power Constrained Design of Multiprocessor Interconnection Networks.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997


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