Jeongwoo Park
Orcid: 0000-0003-3366-2329
According to our database1,
Jeongwoo Park
authored at least 23 papers
between 2007 and 2024.
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Bibliography
2024
Transportable Multispectral Optical-Resolution Photoacoustic Microscopy Using Stimulated Raman Scattering Spectrum.
IEEE Trans. Instrum. Meas., 2024
Enhancing Precision in Eye Surgery: Applanation and Vacuum-Aided Automatic Cornea Needle Insertion System.
IEEE Access, 2024
Morality is Non-Binary: Building a Pluralist Moral Sentence Embedding Space using Contrastive Learning.
Proceedings of the Findings of the Association for Computational Linguistics: EACL 2024, 2024
2023
BIRP: Bitcoin Information Retrieval Prediction Model Based on Multimodal Pattern Matching.
CoRR, 2023
A0.81 mm<sup>2</sup> 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Optimal Implementation Parameters of a Nonlinear Electrical Impedance Tomography Method Using the Complete Electrode Model.
Sensors, 2022
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees.
IEEE J. Solid State Circuits, 2022
Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization.
Proceedings of the Tenth International Conference on Learning Representations, 2022
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Thermal Ablation and High-Resolution Imaging Using a Back-to-Back (BTB) Dual-Mode Ultrasonic Transducer: In Vivo Results.
Sensors, 2021
Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback.
IEEE J. Solid State Circuits, 2020
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020
2019
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2011
An Efficient Processing Scheme for Continuous Queries Involving RFID and Sensor Data Streams.
Proceedings of the Secure and Trust Computing, Data Management and Applications, 2011
2010
IEEE Trans. Consumer Electron., 2010
2008
Co-simulation of SystemC TLM with RTL HDL for surveillance camera system verification.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Consumer Electron., 2007
IEEE Trans. Consumer Electron., 2007
Surveillance camera SOC architecture using one-bit motion detection for portable applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007