Ji-Hoon Kim
Orcid: 0000-0002-4895-0369Affiliations:
- Korea Advanced Institute of Science and Technology (KAIST), School of Electrical Engineering, Daejeon, South Korea
- Kyung-Hee University, Suwon, South Korea (until 2017)
According to our database1,
Ji-Hoon Kim
authored at least 24 papers
between 2018 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
SCRec: A Scalable Computational Storage System with Statistical Sharding and Tensor-train Decomposition for Recommendation Models.
CoRR, April, 2025
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
2024
EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning.
IEEE J. Solid State Circuits, March, 2024
Trinity: In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics.
IEEE Access, 2024
2023
Commun. ACM, July, 2023
Accelerating Large-Scale Graph-Based Nearest Neighbor Search on a Computational Storage Platform.
IEEE Trans. Computers, 2023
A 26.55TOPS/W Explainable AI Processor with Dynamic Workload Allocation and Heat Map Compression/Pruning.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor.
IEEE Micro, 2022
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer.
IEEE J. Solid State Circuits, 2022
Accelerating Large-Scale Graph-based Nearest Neighbor Search on a Computational Storage Platform.
CoRR, 2022
Trinity: End-to-End In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A Dual-Mode Similarity Search Accelerator based on Embedding Compression for Online Cross-Modal Image-Text Retrieval.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
2021
A 0.82 μW CIS-Based Action Recognition SoC With Self-Adjustable Frame Resolution for Always-on IoT Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks.
IEEE J. Solid State Circuits, 2021
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
2020
IEEE J. Solid State Circuits, 2020
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 0.8-V 82.9- $\mu$ W In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
An Ultra-Low-Power Analog-Digital Hybrid CNN Face Recognition Processor Integrated with a CIS for Always-on Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 0.8V 82.9µW In-Ear BCI Controller System with 8.8 PEF EEG Instrumentational Amplifier and Wireless BAN Transceiver.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018