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Jianfeng Luo

Affiliations:
  • Synopsys, Inc., Mountain View, CA, USA


According to our database1, Jianfeng Luo authored at least 4 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
[BibTeX]
[DOI]
Debjit Sinha
,
Jianfeng Luo
,
Subramanian Rajagopalan
,
Shabbir H. Batterywala
,
Narendra V. Shenoy
,
Hai Zhou
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process.
[BibTeX]
[DOI]
Subarna Sinha
,
Jianfeng Luo
,
Charles C. Chiang
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
An IC manufacturing yield model considering intra-die variations.
[BibTeX]
[DOI]
Jianfeng Luo
,
Subarna Sinha
,
Qing Su
,
Jamil Kawa
,
Charles C. Chiang
Proceedings of the 43rd Design Automation Conference, 2006

2005
A layout dependent full-chip copper electroplating topography model.
[BibTeX]
[DOI]
Jianfeng Luo
,
Qing Su
,
Charles C. Chiang
,
Jamil Kawa
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005


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