Jamil Kawa

According to our database1, Jamil Kawa authored at least 25 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
Majority-based Design Flow for AQFP Superconducting Family.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2017
A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2010
Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Who solves the variability problem?
Proceedings of the 47th Design Automation Conference, 2010

2008
Hotspot Based Yield Prediction with Consideration of Correlations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Robust reconfigurable filter design using analytic variability quantification techniques.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Automated design of tunable impedance matching networks for reconfigurable wireless applications.
Proceedings of the 45th Design Automation Conference, 2008

An innovative Steiner tree based approach for polygon partitioning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Design for Manufacturability and Yield for Nano-Scale CMOS
Series on Integrated Circuits and Systems, Springer, ISBN: 978-1-4020-5188-3, 2007

DFM issues for 65nm and beyond.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Accurate modeling of substrate resistive coupling for floating substrates.
ACM Trans. Design Autom. Electr. Syst., 2006

DFM: swimming upstream.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

An IC manufacturing yield model considering intra-die variations.
Proceedings of the 43rd Design Automation Conference, 2006

EDA Challenges in Nano-scale Technology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A layout dependent full-chip copper electroplating topography model.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Custom circuits.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Foundries, EDA vendors, and designers: who shoulders the blame when a design doesn't work in the nano-scale and wireless era?
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Routing resources consumption on M-arch and X-arch.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design automation for mask programmable fabrics.
Proceedings of the 41th Design Automation Conference, 2004

2002
Managing on-chip inductive effects.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk.
Proceedings of the 38th Design Automation Conference, 2001


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