Debjit Sinha

According to our database, Debjit Sinha authored at least 31 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure.

Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Statistical Timing Analysis considering Multiple-Input Switching.

Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2016

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.

Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Generation and use of statistical timing macro-models considering slew and load variability.

Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Practical statistical static timing analysis with current source models.

Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala

Proceedings of the 53rd Annual Design Automation Conference, 2016

Statistical path tracing in timing graphs.

Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya

Proceedings of the 53rd Annual Design Automation Conference, 2016

A distributed timing analysis framework for large designs.

Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

Proceedings of the 53rd Annual Design Automation Conference, 2016

2014

TAU 2014 contest on removing common path pessimism during timing analysis.

Jin Hu, Debjit Sinha, Igor Keller

Proceedings of the International Symposium on Physical Design, 2014

2013

TAU 2013 variation aware timing analysis contest.

Debjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita

Proceedings of the International Symposium on Physical Design, 2013

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization.

Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Timing analysis with nonseparable statistical and deterministic variations.

Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Reversible statistical <i>max/min</i> operation: concept and applications to timing.

Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2009

A Timing-Dependent Power Estimation Framework Considering Coupling.

DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail

IEEE Trans. Very Large Scale Integr. Syst., 2009

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise.

Debjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

Constrained aggressor set selection for maximum coupling noise.

Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Driver waveform computation for timing analysis with multiple voltage threshold driver models.

Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta

Proceedings of the 45th Design Automation Conference, 2008

2007

Advances in Computation of the Maximum of a Set of Gaussian Random Variables.

Debjit Sinha, Hai Zhou, Narendra V. Shenoy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.

Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.

Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Statistical Timing Yield Optimization by Gate Sizing.

Debjit Sinha, Narendra V. Shenoy, Hai Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2006

Statistical Timing Analysis With Coupling.

Debjit Sinha, Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Gate-size optimization under timing constraints for coupling-noise reduction.

Debjit Sinha, Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Yield-Aware Cache Architectures.

Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Advances in Computation of the Maximum of a Set of Random Variables.

Debjit Sinha, Hai Zhou, Narendra V. Shenoy

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.

Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A unified framework for statistical timing analysis with coupling and multiple input switching.

Debjit Sinha, Hai Zhou

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical gate sizing for timing yield optimization.

Debjit Sinha, Narendra V. Shenoy, Hai Zhou

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Yield driven gate sizing for coupling-noise reduction under uncertainty.

Debjit Sinha, Hai Zhou

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Optimal gate sizing for coupling-noise reduction.

Debjit Sinha, Hai Zhou, Chris C. N. Chu

Proceedings of the 2004 International Symposium on Physical Design, 2004

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.

Debjit Sinha, Hai Zhou

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.

Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004