Jie Zhang
Orcid: 0000-0002-7339-9281Affiliations:
- Xi'an Jiaotong University, School of Microelectronics, China
According to our database1,
Jie Zhang
authored at least 22 papers
between 2015 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A 10-Bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-Loop Amplifier and Parallel Conversion Through Comparator Reusing.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2025
A 107.5-dB dynamic range 402-μW event-driven dynamic zoom ADC with voice activity detection function for audio applications.
Microelectron. J., 2025
2024
Artificial Neural Network Based Calibration for a 12 b 250 MS/s Pipelined-SAR ADC With Ring Amplifier in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator.
Microelectron. J., February, 2024
A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision.
Microelectron. J., 2024
2023
A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 9 b 4 GS/s Time-Domain ADC with Self-Reset VTC and Switched-RO TDC Including 8x Hybrid Interpolation.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
An 84dB-SNDR 1-0 Quasi-MASH NS SAR with LSB Repeating and 12-bit Bridge-Crossing Segmented CDAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 6-GHz Bandwidth Input Buffer Based on AC-Coupled Flipped Source Follower for 12-bit 8-GS/s ADC in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
Linearity Boosting Technique with Adaptive Sampling Switch Assisted by Signal Prediction for Multi-Channel ADCs in Standard CMOS Process.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
A 1<sup>st</sup>-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Douglas-Peucker Algorithm Combining Node Importance and Radial Distance Constraints.
Proceedings of the AIAM 2021: 3rd International Conference on Artificial Intelligence and Advanced Manufacture, Manchester, United Kingdom, October 23, 2021
2020
A 12-Cell Battery Monitor IC with 2-Channel 16-bit ADCs and Isolated Bidirectional Data Interface.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
Joint background calibration of gain and timing mismatch errors with low hardware cost for time-interleaved ADCs.
IET Circuits Devices Syst., 2019
2018
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Biomed. Circuits Syst., 2018
2017
A low energy ASIC for triple-chamber cardiac pacemakers with contact resistance measurement.
Microelectron. J., 2017
2015
A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakers.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015