Jin-Gyun Chung

Orcid: 0000-0002-7127-4944

According to our database1, Jin-Gyun Chung authored at least 66 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Real Time Perfect Bit Modification Attack on In-Vehicle CAN.
IEEE Trans. Veh. Technol., December, 2023

2022
Dynamic Rearrangement Compression Algorithm for Intelligent Connected Vehicles.
IEEE Trans. Veh. Technol., 2022

Anomaly information detection and fault tolerance control method for CAN-FD bus network.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Triple ID Flexible MAC for Can Security Improvement.
IEEE Access, 2021

CAN Data Compression Based on Sorting and Mapping Method.
Proceedings of the 18th International SoC Design Conference, 2021

Signature-Based Intrusion Detection System (IDS) for In-Vehicle CAN Bus Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Variable Length MAC for CAN Security Protocol.
Proceedings of the International SoC Design Conference, 2020

CAN Security Protocol Using Modified MAC.
Proceedings of the International SoC Design Conference, 2020

2019
Peak Variation Detection Using Variable Length Moving Average Filter for Defects Inspection Systems.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
4-Bit Data Arrangement Algorithm for CAN Compression.
Proceedings of the International SoC Design Conference, 2018

2017
An Improved Controller Area Network Data-Reduction Algorithm for In-Vehicle Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE.
IEICE Electron. Express, 2017

Improved CAN compression algorithm by data reordering.
Proceedings of the International SoC Design Conference, 2017

2016
Downlink performance of cell edge using cooperative BS for multicell cellular network.
EURASIP J. Wirel. Commun. Netw., 2016

Design of low latency successive cancellation decoder for polar codes.
Proceedings of the International SoC Design Conference, 2016

Low latency IFFT design for 3GPP LTE.
Proceedings of the International SoC Design Conference, 2016

Efficient successive cancellation decoder for polar codes based on frozen bits.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
ISI Free Channel Equalization for Future 5G Mobile Terminal Using Bio-inspired Neural Networks.
Wirel. Pers. Commun., 2015

Signal Constellations of Quasi-Orthogonal Space-Time Codes for MIMO Systems.
Wirel. Pers. Commun., 2015

Efficient controller area network data compression for automobile applications.
Frontiers Inf. Technol. Electron. Eng., 2015

Lattice reduction aided with block diagonalization for multiuser MIMO systems.
EURASIP J. Wirel. Commun. Netw., 2015

Hierarchical fast mode decision algorithm for intra prediction in HEVC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Memory efficient DIT-based SDF IFFT for OFDM systems.
IEICE Electron. Express, 2014

A simple block diagonal precoding for multi-user MIMO broadcast channels.
EURASIP J. Wirel. Commun. Netw., 2014

Design and implementation of CAN data compression algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

CAN compression using signal rearrangement.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Memory efficient IFFT design for OFDM-based applications.
IEICE Electron. Express, 2013

2012
Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications.
IEICE Trans. Commun., 2012

Efficient IFFT architecture design for OFDM applications.
Proceedings of the International SoC Design Conference, 2012

Low power multi-channel capacitive touch sensing unit using capacitor to time conversion method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design of FlexRay-MOST gateway using static segments and control messages.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Integrated protocol-operation-controller design based on FlexRay communication protocol.
Proceedings of the 3rd IEEE International Conference on Network Infrastructure and Digital Content, 2012

2011
Low-complexity filter and interpolator design for ATSC DTV systems.
Proceedings of the International SoC Design Conference, 2011

Low-power FFT design for NC-OFDM in cognitive radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis.
Proceedings of the Multimedia, Computer Graphics and Broadcasting, 2011

2010
Implementation of FlexRay CC and BG protocols with application to a robot system.
Int. J. Comput. Aided Eng. Technol., 2010

Fixed-Width Group CSD Multiplier Design.
IEICE Trans. Inf. Syst., 2010

CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Weighted interpolation using supplementary filter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction.
IEICE Trans. Electron., 2009

2008
Modified CSD group multiplier design for predetermined coefficient groups.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Implementation of FlexRay communication controller protocol with application to a robot system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Constant multiplier design using specialized bit pattern adders.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Efficient IFFT design using mapping method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Adaptive Error Compensation for Low Error Fixed-Width Squarers.
IEICE Trans. Inf. Syst., 2007

Efficient Squarer Design Using Group Partial Products.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Hardware Efficient QR Decomposition for GDFE.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006
Efficient design of modified Booth multipliers for predetermined coefficients.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Design of low-error fixed-width modified booth multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A novel multiplexer-based low-power full adder.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

High-speed assembly FFT implementation with memory reference reduction on DSP processors.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Area Efficient and Low Power Pipelined IIR Filter Design for Intelligent Integrated Photonic System.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

2003
Low error fixed-width CSD multiplier with efficient sign extension.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

High-speed tunable fractional-delay allpass filter structure.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Minimizing switching activity in input word by offset and its low power applications for FIR filters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low-error fixed-width squarer design.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An asynchronous sample-rate converter from CD to DAT.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design.
EURASIP J. Adv. Signal Process., 2002

Design of low error CSD fixed-width multiplier.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Noise generation system using DCT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Efficient ROM size reduction for distributed arithmetic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1995
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Pipelining of lattice IIR digital filters.
IEEE Trans. Signal Process., 1994

1993
The scaled normalized lattice digital filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


  Loading...