Jin-Gyun Chung

According to our database1, Jin-Gyun Chung authored at least 52 papers between 1993 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
An Improved Controller Area Network Data-Reduction Algorithm for In-Vehicle Networks.
IEICE Transactions, 2017

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE.
IEICE Electronic Express, 2017

Improved CAN compression algorithm by data reordering.
Proceedings of the International SoC Design Conference, 2017

2016
Downlink performance of cell edge using cooperative BS for multicell cellular network.
EURASIP J. Wireless Comm. and Networking, 2016

Design of low latency successive cancellation decoder for polar codes.
Proceedings of the International SoC Design Conference, 2016

Low latency IFFT design for 3GPP LTE.
Proceedings of the International SoC Design Conference, 2016

Efficient successive cancellation decoder for polar codes based on frozen bits.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
ISI Free Channel Equalization for Future 5G Mobile Terminal Using Bio-inspired Neural Networks.
Wireless Personal Communications, 2015

Signal Constellations of Quasi-Orthogonal Space-Time Codes for MIMO Systems.
Wireless Personal Communications, 2015

Efficient controller area network data compression for automobile applications.
Frontiers of IT & EE, 2015

Lattice reduction aided with block diagonalization for multiuser MIMO systems.
EURASIP J. Wireless Comm. and Networking, 2015

Hierarchical fast mode decision algorithm for intra prediction in HEVC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Memory efficient DIT-based SDF IFFT for OFDM systems.
IEICE Electronic Express, 2014

A simple block diagonal precoding for multi-user MIMO broadcast channels.
EURASIP J. Wireless Comm. and Networking, 2014

Design and implementation of CAN data compression algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

CAN compression using signal rearrangement.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Memory efficient IFFT design for OFDM-based applications.
IEICE Electronic Express, 2013

2012
Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications.
IEICE Transactions, 2012

Efficient IFFT architecture design for OFDM applications.
Proceedings of the International SoC Design Conference, 2012

Low power multi-channel capacitive touch sensing unit using capacitor to time conversion method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design of FlexRay-MOST gateway using static segments and control messages.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Low-complexity filter and interpolator design for ATSC DTV systems.
Proceedings of the International SoC Design Conference, 2011

Low-power FFT design for NC-OFDM in cognitive radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis.
Proceedings of the Multimedia, Computer Graphics and Broadcasting, 2011

2010
Implementation of FlexRay CC and BG protocols with application to a robot system.
IJCAET, 2010

Fixed-Width Group CSD Multiplier Design.
IEICE Transactions, 2010

CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups.
IEICE Transactions, 2010

Weighted interpolation using supplementary filter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction.
IEICE Transactions, 2009

2008
Modified CSD group multiplier design for predetermined coefficient groups.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Implementation of FlexRay communication controller protocol with application to a robot system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Constant multiplier design using specialized bit pattern adders.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Efficient IFFT design using mapping method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter.
IEEE Trans. on Circuits and Systems, 2007

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients.
IEICE Transactions, 2007

Adaptive Error Compensation for Low Error Fixed-Width Squarers.
IEICE Transactions, 2007

Efficient Squarer Design Using Group Partial Products.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Hardware Efficient QR Decomposition for GDFE.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2004
Design of low-error fixed-width modified booth multiplier.
IEEE Trans. VLSI Syst., 2004

A novel multiplexer-based low-power full adder.
IEEE Trans. on Circuits and Systems, 2004

High-speed assembly FFT implementation with memory reference reduction on DSP processors.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Area Efficient and Low Power Pipelined IIR Filter Design for Intelligent Integrated Photonic System.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

2003
High-speed tunable fractional-delay allpass filter structure.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Minimizing switching activity in input word by offset and its low power applications for FIR filters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An asynchronous sample-rate converter from CD to DAT.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design.
EURASIP J. Adv. Sig. Proc., 2002

Design of low error CSD fixed-width multiplier.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Noise generation system using DCT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Efficient ROM size reduction for distributed arithmetic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1995
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Pipelining of lattice IIR digital filters.
IEEE Trans. Signal Processing, 1994

1993
The scaled normalized lattice digital filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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