Jin Liu

Orcid: 0000-0002-0384-5688

Affiliations:
  • University of Texas at Dallas, Department of Electrical Engineering, USA
  • Georgia Institute of Technology, Atlanta, GA, USA (PhD 1999)


According to our database1, Jin Liu authored at least 48 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2023
A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants.
IEEE J. Solid State Circuits, February, 2023

2022
A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver With Enhanced Current Accuracy.
IEEE J. Solid State Circuits, 2022

A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 3<sup>rd</sup> Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 200mA-Load 0.62fs-FOM Active-Capacitor-Assisted Dual-loop Output Capacitorless Low-Dropout Regulator in Standard 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Diode-Based D-2D DAC Architecture with Leakage Current Compensation for Ultra-low Power Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 1.2-A Dual-Output SC DC-DC Regulator With Continuous Gate-Drive Modulation Achieving ≤0.01-mV/mA Cross Regulation.
IEEE J. Solid State Circuits, 2021

A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter.
IEEE J. Solid State Circuits, 2021

Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit.
Proceedings of the 18th International SoC Design Conference, 2021

A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current Accuracy.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A 9 - 45V Input 2MHz 3-Switch ZVS Step-up / -down Hybrid Converter with 5x Volume Reduction.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A High-Efficiency Low-Profile Zero-Voltage Transition Synchronous Non-Inverting Buck-Boost Converter With Auxiliary-Component Sharing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
High-Speed ADC Quantization with Overlapping Metastability Zones.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer.
Sci. China Inf. Sci., 2017

An open-loop 28GHz 16-phase clock generator in 28nm CMOS.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A New Receiver Architecture for MIMO Beam-Forming Applications.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

2016
A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2014
A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Study of ADC resolution and bandwidth requirement tradeoffs for high-speed data communications.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control.
IEEE J. Solid State Circuits, 2011

An open-loop 10GHz 8-phase clock generator in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders.
IEEE J. Solid State Circuits, 2009

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Gigabit transceivers and building blocks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control.
IEEE J. Solid State Circuits, 2008

2006
An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS.
IEEE J. Solid State Circuits, 2006

A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission.
IEEE J. Solid State Circuits, 2005

A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communication.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A digital power spectrum estimation method for the adaptation of high-speed equalizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Parasitic modeling and analysis for a 1-Gb/s CMOS laser driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

2.45 GHz power and data transmission for a low-power autonomous sensors platform.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A CMOS impulse generator for UWB wireless communication systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An accurate current source with on-chip self-calibration circuits for low-voltage differential transmitter drivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation.
IEEE Trans. Neural Networks, 2002

A robust edge detector for motion detection.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
A fully parallel learning neural network chip for real-time control.
Proceedings of the International Joint Conference Neural Networks, 1999


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