Jing-Ling Yang

According to our database, Jing-Ling Yang authored at least 8 papers between 1999 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Parallel Interleavers Through Optimized Memory Address Remapping.

Jing-Ling Yang

IEEE Trans. Very Large Scale Integr. Syst., 2010

2008

State-Sensitive X-Filling Scheme for Scan Capture Power Reduction.

Jing-Ling Yang, Qiang Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2004

A high-efficiency strongly self-checking asynchronous datapath.

Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Pipelines in Dynamic Dual-Rail Circuits.

Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun

Proceedings of the Integrated Circuit and System Design, 2004

2003

Design for Self-Checking and Self-Timed Datapath.

Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002

A Totally Self-Checking Dynamic Asynchronous Datapath.

Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A self-timed divider using a new fast and robust pipeline scheme.

Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan

IEEE J. Solid State Circuits, 2001

1999

Pipelined Dataflow Architecture of a Small Processor.

Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999