Jing Tian

Orcid: 0000-0003-2402-523X

Affiliations:
  • Nanjing University, School of Electronic Science and Engineering, China


According to our database1, Jing Tian authored at least 39 papers between 2018 and 2024.

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Bibliography

2024
A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA.
IACR Cryptol. ePrint Arch., 2024

2023
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Low-latency Hardware Architecture for VDF Evaluation in Class Groups.
IEEE Trans. Computers, June, 2023

AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

An Efficient Hardware Design for Fast Implementation of HQC.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Efficient Decryption Architecture for Classic McEliece.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

High-Throughput Hardware Implementation for Haraka in SPHINCS+.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation.
IEEE Trans. Computers, 2022

Reduction-Free Multiplication for Finite Fields and Polynomial Rings.
Proceedings of the Arithmetic of Finite Fields - 9th International Workshop, 2022

An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A High-Speed Codec Architecture for Lagrange Coded Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes.
IEEE Commun. Lett., 2021

A High-Speed Architecture for the Reduction in VDF Based on a Class Group.
IACR Cryptol. ePrint Arch., 2021

Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Faster Software Implementation of the SIKE Protocol Based on A New Data Representation.
IACR Cryptol. ePrint Arch., 2020

Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2020

A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders.
IEEE Commun. Lett., 2019

High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2019

Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes.
IEEE Access, 2019

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018


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