Jinming Lu

Orcid: 0000-0002-7134-6514

According to our database1, Jinming Lu authored at least 23 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2025
FLAT-LLM: Fine-grained Low-rank Activation Space Transformation for Large Language Model Compression.
CoRR, May, 2025

FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training.
CoRR, April, 2025

Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization.
CoRR, January, 2025

CDM-QTA: Quantized Training Acceleration for Efficient LoRA Fine-Tuning of Diffusion Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

2023
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization.
IEEE Trans. Neural Networks Learn. Syst., October, 2023

Cathode Shape Design for Steady-State Electrochemical Machining.
Algorithms, February, 2023

An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Data Analysis for Machine Sound Detection: Challenges, Methods, and Future Trends.
Proceedings of the 16th International Congress on Image and Signal Processing, 2023

2022
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2022

An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Evaluations on Deep Neural Networks Training Using Posit Number System.
IEEE Trans. Computers, 2021

A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
A Reconfigurable DNN Training Accelerator on FPGA.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Hardware-Oriented and Memory-Efficient Method for CTC Decoding.
IEEE Access, 2019

Training Deep Neural Networks Using Posit Number System.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

2018
Quantitative Prediction of 3-D Multiple Parameters of Tectonic Fractures in Tight Sandstone Reservoirs Based on Geomechanical Method.
IEEE Access, 2018


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