Jody Maick Matos

Orcid: 0000-0002-7533-6508

According to our database1, Jody Maick Matos authored at least 12 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2020
maj-n Logic Synthesis for Emerging Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Exact Benchmark Circuits for Logic Synthesis.
IEEE Des. Test, 2020

2019
Effective Logic Synthesis for Threshold Logic Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Efficiently Mapping VLSI Circuits With Simple Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Technology Mapping for Circuits with Simple Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Physical Awareness Starting at Technology-Independent Logic Synthesis.
Proceedings of the Advanced Logic Synthesis, 2018

2015
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Open Cell Library in 15nm FreePDK Technology.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Threshold Logic Synthesis Based on Cut Pruning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Deriving Reduced Transistor Count Circuits from AIGs.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Optimization on cell-library design for digital Application Specific Printed Electronics Circuits.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014


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