Vinicius N. Possani

According to our database, Vinicius N. Possani authored at least 16 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Majority-based Design Flow for AQFP Superconducting Family.

Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

LUT-Based Optimization For ASIC Design Flow.

Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Parallel Combinational Equivalence Checking.

Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Exact Benchmark Circuits for Logic Synthesis.

Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas

IEEE Des. Test, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Unlocking fine-grain parallelism for AIG rewriting.

Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Transistor Count Optimization in IG FinFET Network Design.

Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Binary adder circuit design using emerging MIGFET devices.

Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Graph-Based Transistor Network Generation Method for Supergate Design.

Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.

IEEE Trans. Very Large Scale Integr. Syst., 2016

Performance evaluation of optimized transistor networks built using independent-gate FinFET.

Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2014

Exploring Independent Gates in FinFET-Based Transistor Network Generation.

Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

2013

Improving the methodology to build non-series-parallel transistor arrangements.

Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Transistor-level optimization of CMOS complex gates.

Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Efficient transistor-level design of CMOS gates.

Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.

Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012