Walter Lau Neto

According to our database, Walter Lau Neto authored at least 16 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit.

Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Scalable Sequential Optimization Under Observability Don't Cares.

Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù

CoRR, 2023

2022

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal.

Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit.

Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu

CoRR, 2022

Improving LUT-based optimization for ASICs.

Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis.

Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.

Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.

Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Exact Benchmark Circuits for Logic Synthesis.

Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas

IEEE Des. Test, 2020

A Scalable Mixed Synthesis Framework for Heterogeneous Networks.

Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.

Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.

Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017

Sleep convention logic isochronic fork: an analysis.

Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016

A standard cell characterization flow for non-standard voltage supplies.

Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016