Johan Van Praet

According to our database, Johan Van Praet authored at least 7 papers between 1994 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite.

Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet

Proceedings of the International Symposium on System-on-Chip, 2006

2001

Processor modeling and code selection for retargetable compilation.

Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens

ACM Trans. Design Autom. Electr. Syst., 2001

1997

Embedded software in real-time signal processing systems: design technologies.

Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin

Proc. IEEE, 1997

1996

A Graph Based Processor Model for Retargetable Code Generation.

Johan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Describing instruction set processors using nML.

Andreas Fauth, Johan Van Praet, Markus Freericks

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Instruction set definition and instruction selection for ASIPs.

Johan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Chess: retargetable code generation for embedded DSP processors.

Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994