Gert Goossens

According to our database1, Gert Goossens authored at least 31 papers between 1988 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Generation Comp. Syst., 2015

2001
Processor modeling and code selection for retargetable compilation.
ACM Trans. Design Autom. Electr. Syst., 2001

1997
Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis.
IEEE Trans. VLSI Syst., 1997

Multi-thread graph: a system model for real-time embedded software synthesis.
Proceedings of the European Design and Test Conference, 1997

1996
A Graph Based Processor Model for Retargetable Code Generation.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures.
VLSI Signal Processing, 1995

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
VLSI Signal Processing, 1995

Software Synthesis for Real-Time Information Processing Systems.
Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, 1995

Real-time multi-tasking in software synthesis for information processing systems.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

1994
A generalized state assignment theory for transformations on signal transition graphs.
VLSI Signal Processing, 1994

Scheduling with register constraints for DSP architectures.
Integration, 1994

Bit-alignment for retargetable code generators.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Instruction set definition and instruction selection for ASIPs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Data routing: a paradigm for efficient data-path synthesis and code generation.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Design of heterogeneous ICs for mobile and personal communication systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Chess: retargetable code generation for embedded DSP processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Software Synthesis for real-time information processing systems.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1992
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

A generalized state assignment theory for transformation on signal transition graphs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Models for bit-true simulation and high-level synthesis of DSP applications.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1991
Clustering Techniques for Register Optimization During Scheduling Preprocessing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
An integrated automatic design system for complex DSP algorithms.
VLSI Signal Processing, 1990

An efficient microcode compiler for application specific DSP processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Combined hardware selection and pipelining in high performance data-path design.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Open-ended system for high-level synthesis of flexible signal processors.
Proceedings of the European Design Automation Conference, 1990

1989
Loop Optimization in Register-Transfer Scheduling for DSP-Systems.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Architectural strategies for an application-specific synchronous multiprocessor environment.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1988


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