Dirk Lanneer

According to our database1, Dirk Lanneer
  • authored at least 10 papers between 1990 and 2001.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2001
Processor modeling and code selection for retargetable compilation.
ACM Trans. Design Autom. Electr. Syst., 2001

1996
A Graph Based Processor Model for Retargetable Code Generation.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
VLSI Signal Processing, 1995

1994
Instruction set definition and instruction selection for ASIPs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Data routing: a paradigm for efficient data-path synthesis and code generation.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Chess: retargetable code generation for embedded DSP processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1992
Models for bit-true simulation and high-level synthesis of DSP applications.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990
An integrated automatic design system for complex DSP algorithms.
VLSI Signal Processing, 1990

Efficient microcoded processor design for fixed rate DFT and FFT.
VLSI Signal Processing, 1990

Open-ended system for high-level synthesis of flexible signal processors.
Proceedings of the European Design Automation Conference, 1990


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