Dirk Lanneer

According to our database, Dirk Lanneer authored at least 12 papers between 1990 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite.

Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet

Proceedings of the International Symposium on System-on-Chip, 2006

2001

Processor modeling and code selection for retargetable compilation.

Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens

ACM Trans. Design Autom. Electr. Syst., 2001

1997

Embedded software in real-time signal processing systems: design technologies.

Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin

Proc. IEEE, 1997

1996

A Graph Based Processor Model for Retargetable Code Generation.

Johan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.

Gert Goossens, Dirk Lanneer, Marc Pauwels, Francis Depuydt, Koen Schoofs, Augusli Kifli, Marco Cornero, Paolo Petroni, Francky Catthoor, Hugo De Man

J. VLSI Signal Process., 1995

1994

Instruction set definition and instruction selection for ASIPs.

Johan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Data routing: a paradigm for efficient data-path synthesis and code generation.

Dirk Lanneer, Marco Cornero, Gert Goossens, Hugo De Man

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Chess: retargetable code generation for embedded DSP processors.

Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1992

Models for bit-true simulation and high-level synthesis of DSP applications.

Marc Pauwels, Dirk Lanneer, Francky Catthoor, Gert Goossens, Hugo De Man

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990

An integrated automatic design system for complex DSP algorithms.

Jef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, Jan Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man

J. VLSI Signal Process., 1990

Efficient microcoded processor design for fixed rate DFT and FFT.

Francky Catthoor, Dirk Lanneer, Hugo De Man

J. VLSI Signal Process., 1990

Open-ended system for high-level synthesis of flexible signal processors.

Dirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man

Proceedings of the European Design Automation Conference, 1990