According to our database1, Werner Geurts
Legend:Book In proceedings Article PhD thesis Other
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Generation Comp. Syst., 2015
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
Processor modeling and code selection for retargetable compilation.
ACM Trans. Design Autom. Electr. Syst., 2001
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
A Graph Based Processor Model for Retargetable Code Generation.
Proceedings of the 1996 European Design and Test Conference, 1996
Quadratic zero-one programming-based synthesis of application-specific data paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Chess: retargetable code generation for embedded DSP processors.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, August 31, 1994
Loop transformation methodology for fixed-rate video, image and telecom processing applications.
Proceedings of the International Conference on Application Specific Array Processors, 1994
Testability analysis in high level data path synthesis.
J. Electronic Testing, 1993
Quadratic zero-one programming based synthesis of application specific data paths.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
Proceedings of the 29th Design Automation Conference, 1992
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
Proceedings of the 28th Design Automation Conference, 1991