Pierre G. Paulin

According to our database1, Pierre G. Paulin authored at least 71 papers between 1986 and 2014.

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In proceedings 
PhD thesis 


On csauthors.net:


Fast and accurate implementation of Canny edge detector on embedded many-core platform.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Parallel programming patterns for multi-processor SoC: Application to video processing.
ACM Trans. Embed. Comput. Syst., 2013

Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013

Mapping data-intensive applications to an explicitly managed memory architecture: Challenges and solutions.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory.
Proceedings of the International Conference on Compilers, 2013

A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst., 2012

MpAssign: a framework for solving the many-core platform mapping problem.
Softw. Pract. Exp., 2012

On the Verification of a WiMax Design Using Symbolic Simulation.
Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
Proceedings of the Design, Automation and Test in Europe, 2011

Programming challenges & solutions for multi-processor SoCs: an industrial perspective.
Proceedings of the 48th Design Automation Conference, 2011

Combining mapping and partitioning exploration for NoC-based embedded systems.
J. Syst. Archit., 2010

Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett., 2010

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

MpAssign: A framework for solving the many-core platform mapping problem.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst., 2009

Optimizing Configuration and Application Mapping for MPSoC Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

Multicore design is the challenge! what is the solution?
Proceedings of the 45th Design Automation Conference, 2008

Reliable performance analysis of a multicore multithreaded system-on-chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

MPSoC memory optimization using program transformation.
ACM Trans. Design Autom. Electr. Syst., 2007

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs.
IEEE Des. Test Comput., 2007

Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Des. Test Comput., 2007

An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

MPSoC memory optimization for digital camera applications.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A future of customizable processors: are we there yet?
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Two-level tiling for MPSoC architecture.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
IEEE Trans. Very Large Scale Integr. Syst., 2006

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Application-Level Memory Optimization for MPSoC.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Multiprocessor SoC Platform and Tools for Communications Applications.
Proceedings of the Embedded Systems Handbook., 2005

Designing High Quality, Scaleable SoC??s with Heterogeneous Components.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding.
Proceedings of the 2004 Design, 2004

DATE Panel: Chips of the Future: Soft, Crunchy or Hard?
Proceedings of the 2004 Design, 2004

System level design: six success stories in search of an industry.
Proceedings of the 41th Design Automation Conference, 2004

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Network Processing Challenges and an Experimental NPU Platform.
Proceedings of the 2003 Design, 2003

System-on-chip beyond the nanometer wall.
Proceedings of the 40th Design Automation Conference, 2003

FlexWare: A Retargetable Embedded-Software Development Environment.
IEEE Des. Test Comput., 2002

StepNP: A System-Level Exploration Platform for Network Processors.
IEEE Des. Test Comput., 2002

Who Owns the Platform?
Proceedings of the 2002 Design, 2002

Embedded systems technologies for application-specific architecture platforms.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Programming models for network processors (Panel).
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Network processors: a perspective on market requirements, processor architectures and embedded S/W tools.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Towards Application-Specific Architecture Platforms: Embedded Systems Design Automation Technologies.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

The Future of Flexible HW Platform Architectures Panel Discussion.
Proceedings of the 2000 Design, 2000

Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples.
Des. Autom. Embed. Syst., 1998

System-on-a-Chip Cosimulation and Compilation.
IEEE Des. Test Comput., 1997

Compilation Methods for the Address Calculation Units of Embedded Processor Systems.
Des. Autom. Embed. Syst., 1997

ReCode: the design and re-design of the instruction codes for embedded instruction-set processors.
Proceedings of the European Design and Test Conference, 1997

Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor.
Proceedings of the 34st Conference on Design Automation, 1997

Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures.
Proceedings of the 33st Conference on Design Automation, 1996

DSP design tool requirements for embedded systems: A telecommunications industrial perspective.
J. VLSI Signal Process., 1995

Industrial experience using rule-driven retargetable code generation for multimedia applications.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

High-level synthesis and codesign methods: an application to a videophone codec.
Proceedings of the Proceedings EURO-DAC'95, 1995

CodeSyn: a retargetable code synthesis system (abstract).
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Register assignment through resource classification for ASIP microcode generation.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Instruction-Set Matching and Selection for DSP and ASIP Code Generation.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Flexware: A flexible firmware development environment for embedded systems.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Flexible modeling environment for embedded systems design.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Insulin: An Instruction Set Simulation Environment.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

Meta VHDL for Higher Level Controller Modeling and Synthesis.
Proceedings of the VLSI 91, 1991

Force-directed scheduling for the behavioral synthesis of ASICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Algorithms for high-level synthesis.
IEEE Des. Test, 1989

Scheduling and Binding Algorithms for High-Level Synthesis.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Horizontal Partitioning of PLA-based Finite State Machines.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Force-Directed Scheduling in Automatic Data Path Synthesis.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

HAL: a multi-paradigm approach to automatic data path synthesis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986