According to our database1, Joost Briaire authored at least 8 papers between 2007 and 2016.
Legend:Book In proceedings Article PhD thesis Other
IEEE J. Solid State Circuits, 2016
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A novel timing-error based approach for high speed highly linear Mixing-DAC architectures.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.
IEEE J. Solid State Circuits, 2011
Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007